Low-power, transparent optical network interface for high bandwidth off-chip interconnects.
نویسندگان
چکیده
The recent emergence of multicore architectures and chip multiprocessors (CMPs) has accelerated the bandwidth requirements in high-performance processors for both on-chip and off-chip interconnects. For next generation computing clusters, the delivery of scalable power efficient off-chip communications to each compute node has emerged as a key bottleneck to realizing the full computational performance of these systems. The power dissipation is dominated by the off-chip interface and the necessity to drive high-speed signals over long distances. We present a scalable photonic network interface approach that fully exploits the bandwidth capacity offered by optical interconnects while offering significant power savings over traditional E/O and O/E approaches. The power-efficient interface optically aggregates electronic serial data streams into a multiple WDM channel packet structure at time-of-flight latencies. We demonstrate a scalable optical network interface with 70% improvement in power efficiency for a complete end-to-end PCI Express data transfer.
منابع مشابه
A Review of Optical Routers in Photonic Networks-on-Chip: A Literature Survey
Due to the increasing growth of processing cores in complex computational systems, all the connection converted bottleneck for all systems. With the protection of progressing and constructing complex photonic connection on chip, optical data transmission is the best choice for replacing with electrical interconnection for the reason of gathering connection with a high bandwidth and insertion lo...
متن کاملAnalysis of high-bandwidth low-power microring links for off-chip interconnects
Performance scalability of computing systems built upon chip multiprocessors are becoming increasingly constrained by limitations in power dissipation, chip packaging, and the data throughput achievable by the interconnection networks. In particular, today’s systems based on electronic interconnects suffer from a growing memory access bottleneck as the speed at which processor-memory data can b...
متن کاملA Hierarchical Hybrid Optical-Electronic Clos Architecture for Network-on-Chip
With more and more processor cores integrated on a chip, Networks-on-chip (NoC) is emerging as a candidate architecture for multiprocessor systems-on-chip (MPSoC). Traditional metallic interconnects have become the bottleneck of NoC due to the limited bandwidth, long delay, and high power consumption. Optical Network-on-Chip (ONoC) can decrease interconnect delay and provide higher bandwidth wi...
متن کاملNon-Blocking Routers Design Based on West First Routing Algorithm & MZI Switches for Photonic NoC
For the first time, the 4- and 5-port optical routers are designed by using the West First routing algorithm for use in optical network on chip. The use of the WF algorithm has made the designed routers to provide non-blocking routing in photonic network on chip. These routers not only are based on high speed Mach-Zehnder switches(Which have a higher bandwidth and more thermal tolerance than mi...
متن کاملNon-Blocking Routers Design Based on West First Routing Algorithm & MZI Switches for Photonic NoC
For the first time, the 4- and 5-port optical routers are designed by using the West First routing algorithm for use in optical network on chip. The use of the WF algorithm has made the designed routers to provide non-blocking routing in photonic network on chip. These routers not only are based on high speed Mach-Zehnder switches(Which have a higher bandwidth and more thermal tolerance than mi...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
- Optics express
دوره 17 8 شماره
صفحات -
تاریخ انتشار 2009